1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
A well-known semiconductor device is described with reference to FIGS. 10 to 13.
This semiconductor device is a NAND cell-type EEPROM as one of electrically-rewritable and -erasable non-volatile semiconductor devices.
FIG. 10 shows an equivalent circuit of the EEPROM. FIG. 11 illustrates its layout. FIGS. 12 and 13 are sectional views taken along the lines A-Axe2x80x2 and B-Bxe2x80x2, respectively, in FIG. 11.
The NAND cell-type EEPROM is provided with NAND cell sections 4011, 4012, 4021 and 4022 arranged in a matrix, as shown in FIG. 10. Each NAND cell section 40ij (i=1, 2, j=1, 2) has memory cells MC1, MC2, . . . , and MCn. Each memory cell MCi (i=1, . . . ,n) is made up of a stacked transistor having a floating gate 6 and a control gate 8 stacked on a semiconductor substrate 2 via an insulating film 7, as shown in FIGS. 10 and 12. The memory cells MC1, . . . , and MCn in each NAND cell section are connected in series to share the source and drain between adjacent memory cells.
Each NAND cell section 40ij (i=1, 2, j=1, 2) has a drain connected to a bit line BLj via a selection transistor SDTij and a source connected to a source line SLj via a selection transistor SSTij. The source line SLj (j=1, 2) is formed by diffused layer interconnection, having a source-line contact 44 thereon, as shown in FIGS. 11 and 12.
The sources of the selection transistors STD1j and STD2j connected to the NAND cell sections 401j and 402j (j=1, 2) aligned in the column direction are connected to the bit line BLj via a bit-line contact 42j, as shown in FIGS. 10 and 11.
The control gate of the memory cellk (k=1, . . . ,n) of each of the NAND cell sections 4011 and 4012, and 4021 and 4022 aligned in the traverse, respectively, is connected to a word line WLk.
The gates of the selection transistors SDT11 and SDT12 are connected to a selection line SD1, and those of the selection transistors SDT21 and SDT22 are connected to a selection line SD2, as shown in FIG. 10.
The gates of the selection transistors SST11 and SST12 are connected to a selection line SS1, and those of the selection transistors SST21 and SST22 are connected to a selection line SS2, as shown in FIG. 10.
The NAND cell section 40ij (i=1, 2, j=1, 2), the selection transistors SDTij (i=1, 2, j=1, 2) and SSTij (i=1, 2, j=1, 2) and also a silicon nitride film 12 are covered with an interlayer dielectric 22 formed on which are the bit linei (i=1, 2), as shown in FIGS. 12 and 13.
Each memory cell, selection transistor and also a element isolation region 4 of the well-known EEPROM are covered with the silicon nitride film 12 that will act as a barrier insulating film for contact formation.
This structure offers miniaturization of bit-line and source-line contact regions (diffused layer regions) and protection of the element isolation region 4 including silicon oxide adjacent to the contact regions from dielectric breakdown which would otherwise occur, such that, a contact in the interlayer dielectric 22, for example, a contact 422 punches therethrough and electrically contact with the semiconductor substrate 2, as illustrated in FIG. 13.
As illustrated in FIG. 14, each memory cell of the well-known EEPROM is formed such that an interface 82 between the silicon nitride film 12 and a silicon oxide film 5a on a diffused layer 9 is located under (at the substrate 2 side) an interface 84 between the floating gate 6 and a gate insulating film 5.
As described, each memory cell of the well-known semiconductor device is covered with a silicon nitride film.
The well-known semiconductor device has, however, drawbacks as discussed below.
First of all, as illustrate in FIG. 14, in data-writing/erasing, carriers pass through the gate insulating film 5 and some of them are trapped by the silicon nitride film 12 close to the gate insulating film 5 and also the interface 82 between the silicon nitride film 12 and the silicon oxide film 5a. 
This causes induction of carriers of the opposite polarity on the surface of the diffused layer 9 to increase parasitic resistance to the layer 9, thus reducing a transistor driving force. Increase in parasitic resistance to the diffused layer of a NAND cell-type EEPROM poses a big problem because it has memory cells series-connected via the layer 9.
Such parasitic resistance further increases to affect miniaturization of memory cells when decreasing a dose of ions to the diffused layer for reduction of short channel effect.
A numeral 10 in FIG. 14 represents a silicon oxide film formed by post-oxidation for recovery from damage to the device caused by gate formation.
Another drawback to the well-known semiconductor device is that hydrogen involved in the silicon nitride film 12 degrades the gate insulating film 5 close to the film 12, thus lowering reliability in transistor performance.
A purpose of the present invention is to provide a semiconductor device that is protected from reduction in transistor driving force and reliability.
The present invention provides a semiconductor device including: at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode; and a barrier insulating film formed so as to cover the transistor and the diffused layer, wherein a height from a surface of the semiconductor substrate to the barrier insulating film is greater than a height from the surface of the semiconductor substrate, of an interface between the gate insulating film and the gate electrode.
An inter-film may be formed between the diffused layer and the barrier insulating film.
The inter-film may be made of a material different from that of the barrier insulating film.
The semiconductor substrate may be made of silicon and the barrier insulating film may be made of silicon nitride.
The inter-film may include silicon oxide.
The inter-film may be made of a conductive material.
The inter-film may include silicon doped impurities of the same conductive type as that of the diffused layer.
The inter-film may include a silicide.
The inter-film is preferably thicker than the gate insulating film.
The present invention provides a semiconductor device including: at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode; and a barrier insulating film formed so as to cover the transistor and the diffused layer, a distance between a side face of the gate electrode and the barrier insulating film being larger than a thickness of the gate insulating film.
The transistor may make up of a memory cell of an EEPROM.